USB2 Tape Interface V0.2 Jul 11, 2006 Introduction ------------ This is a design for a magnetic tape interface capable of interfacing to magnetic and magnetorestrictive transducers. The goal is to make a software programmable interface capable of reading 1 to 9 channels of tape data and attaching it to modified tape transports for recovery of tapes incapable of being read on existing equipment. Initial transport mechanisms will be the DEC TU56 DECtape drive and Qualstar 105x 1/2" tape transport. At the simplest level, it captures magnetic flux transitions in the analog domain from up to nine channels and passes them back to a computer for analysis through a USB2 interface. Since there is an FPGA in the data path, signal processing can be applied to this raw data stream. History ------- This is an evolutionary design, started in 2001. The original design used two-channel 20MHz 10 bit A/D converters with parallel outputs, and a synchronous FIFO interfaced to an IDE connector. A PCB was fabricated, but was never built. At about this same time, a parallel development effort started in Canada to use an 18 track magnetorestrictive head from an IBM 3480 tape drive and a Qualstar 105x series transport. The Qualstar uses a very simple tape transport mechanism which had some documentation available. Magnetorestrictive heads have properties that make them attractive for recovery of tapes in poor condition. A proof of concept for this drive was developed in 2004 and 2005 which uses a custom read channel and a Ubicom 2022 with a 10mbit Ethernet interface. No further details on the implementation have been made available. In July, 2006 after several months of attempts to contact the implementor in Canada, a design was started with the explicit goal of making the design completely open. Sixteen addtional 3480 head assemblies were obtained from used drives. The firmware for the 105x transport has been disassembled, analysis of the motor transport code has started, and a request has been made to a local machinist for a head shim to adapt the 3480 head to the 105x transport. For initial tests, the existing 9-track head on the 105x will be used. As a vehicle for experimentation, a fpga4fun SAXO board with FLASHY-D two channel 8 bit A/D converter was obtained. This was the closest example of a low cost data aquistion system that was readily available. A new 9 channel analog board will be developed to replace the FLASHY-D for the tape reading application. Two ICs were found which appear to be perfect for this application. The Philips TZA1000 QIC read-write amplifer and TI ADS7887 10 bit A/D Converter. Block Diagram ------------- +----------------+ | MR or | | Magnetic +<-+ | Transducer | | +----+-----+-----+ | V V | MR Bias 1 2 3 4 5 6 7 8 9 +----+-----+-----+ | | | | | | | | | | | TZA1000 | | +-+-+-+-+-+-+-+-+-+------+ | Preamp / +--+ | I2C chan enables | | AGC / MR Bias | | PCA9555 16 Bit I/O | | +--< 24 MHz clk | | +-------+-----++-+ +-----------+------------+ | |+-----< I2C chan enable | V +------------------------------------------------------------------+ +-------+--------+ | | ADS7887 | | | 10 Bit Serial +--< 24 Mhz CLK | | A/D 1.25MSamp | | +----+--+--------+ | data V ^ start | | | | | | | | | | | | | | | | | tape intf board +----+--+------------+--+---+--+---+--+---+--+---+--+---+--+---+--+---+--+----+ | ------------- | CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 | | saxo board | | | | Altera EP1C3T100 FPGA | | | | | +--------------------------------------+--------------------------------------+ | | | | | +--------------------------------------+--------------------------------------+ | | | | | Cypress CY7C68013 EZ-USB FX2 I2C +--+ | (56 pin) | +------+----------------------------------------------------------------------+ | | | USB2 Overview -------- TZA1000/ADS7887 combo produces nine streams of serial data. In its simplest form, the FPGA just reformats the incoming streams so they appear as a byte stream of samples. Specific channel algorithms can be developed on the host side, then pushed back into the FPGA. The A/D start lines are separated out per channel to permit channel deskewing inside the FPGA with a resolution of 41nS (24MHz). The system runs at the maximum sampling rate of the A/D converter. Lower sampling rates are easily taken care of by the FPGA by either discarding or averaging the incoming samples. The TZA1000 has an internal bias generator for magnetorestrictive read heads, a preamp with 34 or 40db of gain, AGC stage, and low pass filter. Parameters are programmable via I2C. It should be possible to use either magnetic or magnetorestrictive transducers with jumpers to disconnect the MR bias supply. Since the TZA1000 has no way to select different I2C adrs, a set of nine SDEN lines is required. A PCA9555 16 bit I/O port is used on the tape interface board for this purpose. The entire system will run off a common 24MHz clock to avoid clock domain problems. 9 vs 18 Channels ---------------- The first idea was to handle a worst-case of all 18 possible channels from a 3480 MR head stack. This is probably overkill, since it doubles the I/O resources needed from the FPGA. It will probably be adequate to just pick the best match of an incoming track to one of the 18 possible MR tracks. It may also be possible to synchronize two USB tape interfaces to capture all 18 tracks of data if needed. Motor control of the Qualstar may be possible by the EZ-USB as well, once the motor control algorithm and time available in the EZ-USB is better understood. DECtape Implementation ---------------------- This is the n-th iteration of a low-level interface for reading DECtapes and LINCtapes. The first attempt sampled clock, mark, and data tracks through a PC parallel port. This was not reliable due to the impossibility of completely disabling interrupts on the host. A second design was built in June, 2006 which used the clock track to load a 4K FIFO. The interrupt problem was taken care of, and software was written to recover data from many DECtapes, but the known problem of the poor quality of the analog G888 read channel design has caused problems with recovering the most valuable (ie. oldest) tapes. It was also necessary to vary the sampling point of the clock, which causes problems as the sample point varies as tape speed varies (DECtapes are not constant velocity). Since DECtape uses Manchester encoding, it should be possible to do away with the use of the clock track completely, and recover the data on a per-channel basis with deskewing once the G888 read channel has been replaced with a more modern design. Qualstar Implementation ----------------------- TBD 1/2" Tape Analog Data Transfer Rates / Data Set Sizes ----------------------------------------------------- 2400' x 12 = 28800 inches of tape per reel 28800 / 25 = 1152 secs (19.2 mins) for end-end traversal at 25 inches/sec 1.25mSamp/Sec x 9 x 2 = 22.5 mbytes/sec (9 channels, 2 bytes/sample) 22500000 x 1152 = 25.92gb (max aquisition speed 9 channels 2 bytes/sample 25 ips 2400' tape) 800bpi x 25ips x 9 = 180000 samples/sec (9 channels w/o oversampling) 800bpi x 25ips x 7 = 140000 samples/sec (7 channels w/o oversampling) 1152 x 180000 x 2 = 414.72 mbytes (9 trk 2 bytes/sample w/o oversampling) 1152 x 140000 x 2 = 322.56 mbytes (7 trk 2 bytes/sample w/o oversampling) References ---------- TZA1000 QIC read-write amplifer, Philips 1998 Mar 17 10/8 Bit, 1.25-MSPS, Micro Power, Miniature SAR Analog-To-Digital Converters, TI June 2005 FPGA4FUN SAXO board documentation Altera Cyclone FPGA documentation Cypress CY7C68013 user's manual